AMD GPU Architecture Notes

RDNA and CDNA references for kernel and compiler development

Architecture differences are useful only with their applicable targets, instruction variants, and evidence. These references keep those conditions next to the conclusions, with diagrams for the mappings and data paths that benefit from a visual explanation.

Choose your starting point. Read an architecture comparison for hardware behavior, or a compiler article for LLVM dependency handling. The compiler articles introduce their own targets and operands; you can read them independently.

RDNA: architecture and LLVM

Hardware differences

RDNA 3, RDNA 3.5, and RDNA 4 compares matrix instructions, lane and register layouts, cross-lane operations, memory movement, and synchronization.

• Quick comparison
• WMMA layouts and formulas
• Global, LDS, and VGPR data paths
• Evidence status and limits

LLVM handling

LLVM on RDNA: WMMA dependencies and waits follows the compiler’s register-overlap fixes, memory waits, optional ALU delays and inline-assembly boundaries at a pinned revision.

• Findings and scope
• Dependency cases

CDNA: architecture and LLVM

Hardware differences

CDNA 3 and CDNA 4 compares gfx942 and gfx950, with particular attention to MFMA shapes, FNUZ versus OCP FP8, LDS resources, data movement, and synchronization.

• Quick comparison
• MFMA lane and register layouts
• Memory paths and copy stride
• Evidence status and limits
• Migration priorities

LLVM handling

LLVM on CDNA: MFMA dependencies and waits covers target interfaces, physical register overlap, wait-state accounting, memory readiness and developer checks.

• Findings and scope
• Shared FP16 dependency cases

Research scope

This topic covers AMD’s RDNA and CDNA architectures. The two families have separate target scopes and evidence. Shared presentation does not imply shared hardware behavior.

Each document distinguishes ISA requirements, compiler behavior at a pinned revision, and properties confirmed only at the presentation level. Source review is separate from compilation, GPU execution, and performance validation.